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DATA SHEET
TDA8260TW Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
Product specification Supersedes data of 2003 Jun 11 2004 Sep 03
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
FEATURES * Direct conversion Quadrature Phase Shift Keying (QPSK) and 8-Phase Shift Keying (8PSK) demodulation (Zero-IF) * Frequency range: 950 to 2175 MHz * High level asymmetrical RF input * 0 to 50 dB variable gain with AGC control * Loop-controlled 0 to 90 phase shifter * High AGC linearity (<1 dB per bit with an 8-bit DAC), AGC voltage variable between 0 and 3 V * Integrated 5th-order matched baseband filters for in-phase (I) and quadrature (Q) signal paths * Controlled I-to-Q gain balance * I2C-bus controlled PLL frequency synthesizer * Low phase noise * Operation from a 4 MHz crystal (allowing the use of an SMD crystal) * Five frequency steps from 125 kHz to 2 MHz * Crystal frequency output to drive the demodulator IC * Compatible with 5, 3.3 and 2.5 V I2C-bus * Fully compatible and easy to interface with Philips Semiconductors family of digital satellite demodulators * +5 V DC supply voltage * 38-pin high heat dissipation package. APPLICATIONS * Direct Broadcasting Satellite (DBS) QPSK demodulation * Digital Video Broadcasting (DVB) QPSK demodulation * BS digital 8PSK demodulation. GENERAL DESCRIPTION The direct conversion QPSK demodulator is the front-end receiver dedicated to digital TV broadcasting, satisfying both DVB and DBS TV standards. The wide range oscillator (from 950 to 2175 MHz) covers the American, European and Asian satellite bands, as well as the SMA-TV US standard. The Zero-IF concept discards traditional IF filtering and intermediate conversion techniques. It also simplifies the signal path.
TDA8260TW
Optimum signal level is guaranteed by gain-controlled amplifiers in the RF path. The 0 to 50 dB variable gain is controlled by the signal returned from the Satellite Demodulator and Decoder (SDD) and applied to pin AGCIN. The PLL synthesizer is built on a dual-loop concept. The first loop controls a fully integrated L-band oscillator, using as a reference the LC VCO which runs at a quarter of the synthesized frequency. The second loop controls the tuning voltage of the VCO and improves the phase noise of the carrier within the loop bandwidth. The step size is equal to the comparison frequency. The input of the main divider of the PLL synthesizer is connected internally to the VCO output. The comparison frequency of the second loop is obtained from an oscillator driven by an external 4 MHz crystal. The 4 MHz output available at pin XTOUT may be used to drive the crystal inputs of the SDD, thereby saving an additional crystal in the application. Both the divided and the comparison frequencies of the second loop are compared in a fast phase detector which drives the charge pump. The TDA8260TW includes a loop amplifier with an internal high-voltage transistor to drive an external 33 V tuning voltage. Control data is entered via the I2C-bus. The I2C-bus voltage can be 5.0, 3.3 or 2.5 V, thus allowing compatibility with most existing microcontrollers. A 5-byte frame is required to address the device and to program the main divider ratio, the reference divider ratio, the charge pump current and the operating mode. A flag is set when the loop is `in-lock', this can be read during READ operations, as well as the Power-on reset flag. The device has four selectable I2C-bus addresses. The selection is done by applying a specific voltage to pin AS. This feature gives the possibility to use up to four TDA8260TW ICs in the same system.
2004 Sep 03
2
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
Performance summary TDA8260TW performance: * Noise figure at maximum gain = +18 dB * High linearity; IP2 = +19 dBm and IP3 = +14 dBm * Low phase noise on baseband outputs: -78 dBc/Hz (foffset = 1 and 10 kHz; fCOMP = 1 MHz) * 0 to 50 dB variable gain with AGC control * AGC linearity <1 dB/bit with an 8-bit DAC * Maximum I-to-Q amplitude mismatch = 1 dB * Maximum I-to-Q phase mismatch = 3 * Signal rates from 1 to 45 MSymbol/s. QUICK REFERENCE DATA SYMBOL VCC ICC fosc Eq PARAMETER supply voltage supply current oscillator frequency quadrature error (absolute value) VAGC = 1.5 V; Vo(p-p) = 750 mV; measured in baseband CONDITIONS - 950 - MIN. 4.75
TDA8260TW
System performance, for example, in a tuner application with the IC placed after a low-cost discrete LNA (see Fig.11): * Noise figure at maximum gain = 8 dB * High linearity; IP2 = +15 dBm and IP3 = +5 dBm * 0 to 50 dB variable gain with AGC control. Specification limitation The content of this specification is applies to the device TDA8260TW with versions C2 and above. Version C1 is not covered by this document. Please contact your Philips semiconductors representative for further information.
TYP. 5.0 155 - 0
MAX. 5.25 - 2175 3
UNIT V mA MHz deg
Vo(p-p) LPFCO n
recommended output voltage (peak-to-peak value) LPF cut-off frequency phase noise on baseband outputs foffset = 1 and 10 kHz; fCOMP = 1 MHz with appropriate loop filter and charge pump setting AGC range AC output voltage on pin XTOUT (peak-to-peak value) ambient temperature VAGC = 0 to 3 V T2 = 1, T1 = 0, T0 = 0; driving a load of CL = 10 pF, RL = 1 M
- - -
750 36 -
- - -78
mV MHz dBc/Hz
Gv VXTOUT(p-p)
48 500
50 650
- -
dB mV
Tamb
-20
-
+85
C
ORDERING INFORMATION TYPE NUMBER TDA8260TW PACKAGE NAME DESCRIPTION VERSION SOT633-3
HTSSOP38 plastic thermal enhanced thin shrink small outline package; 38 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
2004 Sep 03
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Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
BLOCK DIAGRAM
TDA8260TW
handbook, full pagewidth
RFGND2 BIASN 11 6
CAP1 CAP2 27 26
BBGND1 15
IOUT QBBIN VCC(BB) LP1 LP2 QOUT IBBIN BBGND2 17 12 13 25 14 16 23 24 22 21 n.c. IBBOUT IIN QIN QBBOUT
RFA RFB RFGND1 VCC(RF) VCOGND VCC(VCO)
9 10 7 8 28 31 AGC CONTROL
20 19 18
5
AGCIN
TKA TKB
30 29 VCO FAST PHASE/ FREQUENCY COMPARATOR
Q
I integrated oscillator
DIVIDE-BY-4 15-BIT DIVIDER f DIV XT1 XT2 1 2 OSCILLATOR f XTAL REFERENCE DIVIDER
TDA8260TW
DIGITAL PHASE COMPARATOR f COMP CHARGE PUMP
33 V AMP
34
CP
PLLGND VCC(PLL)
4 3
33
VT
38 37 36 35 32
XTOUT
SDA SCL AS BVS
I2C-BUS
CONTROL LOGIC AND LATCH
POWER-ON RESET
MGU790
Fig.1 Block diagram.
2004 Sep 03
4
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
PINNING INFORMATION SYMBOL XT1 XT2 VCC(PLL) PLLGND AGCIN BIASN RFGND1 VCC(RF) RFA RFB RFGND2 LP1 LP2 QOUT BBGND1 QBBIN VCC(BB) QBBOUT QIN IIN IBBOUT n.c. IBBIN BBGND2 IOUT CAP2 CAP1 VCOGND TKB TKA VCC(VCO) BVS VT CP AS SCL SDA XTOUT PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 4 MHz crystal oscillator input 1 4 MHz crystal oscillator input 2 supply voltage for PLL circuit (+5 V) ground for PLL circuit AGC input from satellite demodulator and decoder RF isolation input (+5 V) ground 1 for RF circuit supply voltage for RF stage (+5 V) RF signal input A RF signal input B ground 2 for RF circuit low-pass filter loop filtering output low-pass filter loop filtering input quadrature output for AC coupling to pin 16 ground 1 for baseband stage quadrature baseband AC-coupled input from pin 14 supply voltage for baseband stage (+5 V) DESCRIPTION
TDA8260TW
quadrature baseband output to satellite demodulator and decoder quadrature input for auto-amplitude matching in-phase input for auto-amplitude matching in-phase baseband output to satellite demodulator and decoder not connected in-phase AC-coupled baseband input from pin 25 ground 2 for baseband stage in-phase output for AC-coupling to pin 23 amplitude matching loop filtering output 2 amplitude matching loop filtering output 1 ground for VCO circuit VCO tank circuit input B VCO tank circuit input A supply voltage for VCO circuit (+5 V) bus voltage select input tuning voltage output for VCO charge pump output address selection input I2C-bus clock input I2C-bus data input/output 4 MHz crystal oscillator output to satellite demodulator and decoder
2004 Sep 03
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Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
FUNCTIONAL DESCRIPTION
TDA8260TW
handbook, halfpage
The TDA8260TW contains the core of the RF analog part of a digital satellite receiver. The signal coming from the Low Noise Block (LNB) is coupled through a Low Noise Amplifier (LNA) to the RF inputs. The internal circuitry performs the Zero-IF quadrature frequency conversion and the two in-phase (IBBOUT) and quadrature (QBBOUT) output signals can be used directly to feed a Satellite Demodulator and Decoder circuit (SDD).
XT1 XT2 1 2 3 4 5 6 7 8 9 38 XTOUT 37 SDA 36 SCL 35 AS 34 CP 33 VT 32 BVS 31 VCC(VCO) 30 TKA 29 TKB
VCC(PLL) PLLGND AGCIN BIASN RFGND1 VCC(RF) RFA
The TDA8260TW has a gain-controlled amplifier in the converter circuit. The gain is controlled by the AGCIN input from the SDD. An external VCO tank circuit is connected between pins TKA and TKB. The main elements of the external tank circuit are an SMD coil and a varactor diode. The tuning voltage of 0 to 30 V covers the whole frequency range from 237.5 to 543.75 MHz. The internal loop controls a fully integrated VCO to cover the range 950 to 2175 MHz. The VCO provides both in-phase and quadrature signals to drive the two mixers. Except for the 4 MHz crystal and the loop filter, all circuit components necessary to control the varactor-tuned oscillator are integrated in the TDA8260TW. The tuning circuit includes a fast phase detector with a high comparison frequency in order to achieve the lowest possible level of phase noise in the local oscillator. The fDIV output of the15-bit programmable divider passes through the fast phase comparator where it is compared in both phase and frequency with the comparison frequency (fCOMP). The frequency fCOMP is derived from the signal present at the XT1/XT2 pins (fXTAL) divided-down by the reference divider. The buffered XTOUT signal can drive the crystal frequency input of the SDD, thereby saving a crystal in the application. The output of the phase comparator drives the charge pump and loop amplifier section. The loop amplifier includes a high voltage transistor to handle the 30 V tuning voltage at pin VT, this drives a variable capacitance diode in the external circuit of the voltage controlled oscillator. Pin CP is the output of the charge pump. The loop filter is connected between pins CP and VT and the post-filter section is connected between pin VT and the variable capacitance diode. For test and alignment purposes, it is possible to release the tuning voltage output and apply an external voltage to pin VT, also to select the charge pump function to sink current, source current or to be switched off.
RFB 10
TDA8260TW
RFGND2 11 LP1 12 LP2 13 QOUT 14 BBGND1 15 QBBIN 16 VCC(BB) 17 QBBOUT 18 QIN 19
MGU791
28 VCOGND 27 CAP1 26 CAP2 25 IOUT 24 BBGND2 23 IBBIN 22 n.c. 21 IBBOUT 20 IIN
Fig.2 Pin configuration.
2004 Sep 03
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Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
PROGRAMMING The programming of the TDA8260TW is performed through the I2C-bus. The read/write selection is made through the R/W bit (address LSB). The TDA8260TW fulfils the I2C-bus fast mode, according to the Philips I2C-bus specification, see document "9398 393 40011". I2C-bus voltage The I2C-bus lines SCL and SDA can be connected to an I2C-bus system tied either to 2.5, 3.3 or 5.0 V, that will allow direct connection to most existing microcontrollers. The choice of the threshold voltage for the I2C-bus lines is made with pin BVS that needs to be left open-circuit, connected to supply voltage or connected to ground; see Table 1. Table 1 I2C-bus voltage selection PIN BVS GND Open-circuit VCC Table 2 I2C-bus write data format BYTE Programmable address Programmable divider (PD1) Programmable divider (PD2) Control data (CD1) Control data (CD2) Notes 1. MSB is transmitted first. 2. X = undefined. 3. Acknowledge bit (A). (MSB)(1) 1 0 N7 1 C1 1 N14 N6 T2 C0 0 N13 N5 T1 X 0 N12 N4 T0 X BITS(2) 0 N11 N3 R2 X MA1 N10 N2 R1 X MA0 N9 N1 R0 X I2C-BUS VOLTAGE (V) 2.5 3.3 5 I2C-bus write mode
TDA8260TW
I2C-bus write mode: R/W = logic 0; see Table 2. After transmission of the address (first byte), four data bytes can be sent to fully program the TDA8260TW. The transmission sequence is one address byte followed by four data bytes PD1, PD2, CD1 and CD2. The I2C-bus transceiver has an auto-increment facility that permits the TDA8260TW to be programmed within a single transmission. The TDA8260TW can be partly programmed provided that the first data byte following the address is PD1 or CD1. The first bit of the first data byte transmitted indicates whether PD1 (first bit = logic 0) or CD1 (first bit = logic 1) will follow. Additional data bytes can be entered without the need to re-address the device until an I2C-bus STOP condition is sent by the controller. Each byte is loaded after the corresponding 8th clock pulse. Programmable divider data (contents of PD1 and PD2) become valid only after the 8th clock pulse of PD2, or after a STOP condition if only PD1 needs to be programmed.
(LSB) 0 N8 N0 X X
ACK(3) A A A A A
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Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
PROGRAMMABLE ADDRESSES The programmable address bits MA1 and MA0 offer the possibility of having up to four TDA8260TW devices in the same system. The relationship between the voltage applied to pin AS and the value of bits MA1 and MA0 is given in Table 3. Table 3 I2C-bus address selection VAS 0 to 0.1VCC open-circuit 0.4VCC to 0.6VCC 0.9VCC to VCC MA1 0 0 1 1 MA0 0 1 0 1 Table 5 R2 0 0 0 0 1 1 1 1 Reference divider ratio R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 32 16 REFERENCE DIVIDER
TDA8260TW
Five reference divider ratios allow the adjustment of the comparison frequency to different values depending on the compromise that has to be found between step size and phase noise. The reference divider ratios and the corresponding comparison frequencies are programmed using bits R2, R1 and R0; see Table 5.
DIVIDER RATIO 2 4 8
COMPARISON FREQUENCY 2 MHz 1 MHz 500 kHz
PROGRAMMABLE MAIN DIVIDER RATIO Program bytes PD1 and PD2 contain the fifteen bits N14 to N0 that set the main divider ratio. The ratio N = N14 x 214 + N13 x 213 +...+ N1 x 2 + N0. OPERATING AND TEST MODES The mode of operation is set using bits T2, T1 and T0 in control byte CD1; see Table 4. Table 4 T2 0 0 0 0 1 1 1 1 Note 1. Status at power-on: the tuning voltage output is released and pin VT is in the high-impedance state. Mode selection T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 MODE normal operation POR state = CP
1/ 2
not allowed not allowed 250 kHz not allowed 125 kHz
CHARGE PUMP CURRENT Four values of charge pump current can be chosen using bits C1 and C0; see Table 6. Table 6 C1 0 0 1 1 Charge pump current C0 0 1 0 1 TYPICAL CHARGE PUMP CURRENT ABSOLUTE VALUES (A) 420 900 1360 2320
XTOUT OFF fXTAL
1/ 2
sink(1)
x fDIV
x fDIV
CP sink normal operation 2 x fref CP OFF CP source
fXTAL fXTAL 2 x fref fXTAL fXTAL
2004 Sep 03
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Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
I2C-bus read mode I2C-bus read mode: R/W = logic 1 (address LSB; see Table 7). When a read sequence is started, all eight bits of the status byte must be read. Data can be read from the TDA8260TW by setting the R/W bit to logic 1. After recognition of its slave address, the TDA8260TW generates an acknowledge pulse and transfers the status byte onto the SDA line (MSB first). Data is valid on the SDA line when the SCL clock signal is HIGH.
TDA8260TW
A second data byte can be read from the TDA8260TW if the microcontroller generates an acknowledge on the SDA line. End of transmission will occur if no acknowledge is received from the microcontroller. The TDA8260TW will then release the data line to allow the microcontroller to generate a STOP condition. The POR flag (Power-on reset) is set to logic 1 at power-on and when VCC goes below 2.7 V. It is reset to logic 0 when an end-of-data condition is detected by the TDA8260TW (end of a READ sequence). The in-lock flag FL indicates that the loop is phase-locked when set to logic 1.
Table 7
I2C-bus read data format BYTE (MSB) 1 POR 1 FL(2) 0 X(3) 0 X(3) BITS 0 X(3) MA1 X(3) MA0 X(3) (LSB) 1 X(3) ACK(1) A -
Address Status byte Notes 1. Acknowledge bit (A).
2. FL is valid only in normal mode. 3. X can be 1 or 0 and needs to be masked in the microcontrollers' software; MSB is transmitted first. POWER-ON RESET Power-on reset flag POR = 1 at power-on. At power-on, or when the supply voltage drops below 2.7 V, internal registers are reset as shown in Table 8. Table 8 Status at Power-on reset BYTE Programmable divider (PD1) Programmable divider (PD2) Control data (CD1) Control data (CD2) Note 1. X = not set. (MSB) 0 N7 = X 1 C1 = X N14 = X N6 = X T2 = 0 C0 = X N13 = X N5 = X T1 = 0 X BITS(1) N12 = X N4 = X T0 = 1 X N11 = X N3 = X R2 = X X N10 = X N12 = X R1 = X X N9 = X N1 = X R0 = X X (LSB) N8 = X N0 = X X X
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Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); see note 1. SYMBOL VCC Vi(max); Vo(max) Vi(SDA); Vo(SDA) Vi(SCL) Vo(tune) Tamb Tstg Tj(max) tsc(max) Note supply voltage data input or data output voltage clock input voltage tuning voltage output ambient temperature IC storage temperature maximum junction temperature maximum short-circuit time; each pin; short-circuit to VCC or GND PARAMETER MIN. -0.3 -0.3 -0.3 -0.3 -20 -40 - -
TDA8260TW
MAX. +6.0 VCC + 0.3 +6.0 +6.0 +35 +85 +150 150 10
UNIT V V V V V C C C s
maximum input or output voltage on all pins except SDA, SCL and VT -0.3
1. Maximum ratings cannot be exceeded, not even momentarily, without causing irreversible damage to the IC. Maximum ratings cannot be accumulated. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices"). ESD specification: * Every pin withstands 2000 V in the ESD test in accordance with JEDEC specification EIA/JESD-A114A, HBM model (category 2); except pins SCL (pin 36), VT (pin 33) and VCC(RF) (pin 8). * Identically every pin withstands 200 V in the ESD test in accordance with JEDEC specification EIA/JESD22-A115A, MM model (category B); except pins TKA (pin 30) and TKB (pin 29). PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 39 UNIT K/W
2004 Sep 03
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Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
TDA8260TW
CHARACTERISTICS Tamb = 25 C; VCC = 5 V; RL = 1 k and Vo(p-p) = 750 mV on baseband output pins IBBOUT and QBBOUT; unless otherwise specified. SYMBOL Supply VCC ICC VCC(POR) supply voltage supply current supply voltage threshold for POR active 4.75 - - 5.00 155 2.7 5.25 - - V mA V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Performance from RF inputs to I, Q outputs (from pins RFA, RFB to pins IBBOUT, QBBOUT) PL(LO) LO power leakage through pins RFA and RFB - 55 48 - -75 57 50 750 19 14 18 - 0 - - - - - - - 1 3 dBm dB dB mV dBm dBm dB dB deg
Gv(RF-BBOUT)(max) maximum voltage gain from pins VAGC = 3 V RFA, RFB to IBBOUT, QBBOUT Gv Vo(p-p) IP2i IP3i F Gv(IQ) Eq AGC range output voltage (peak-to-peak value) 2nd-order interception point 3rd-order interception point noise figure voltage gain mismatch between I and Q quadrature error (absolute value) voltage gain ripple for I or Q group delay ripple for I or Q ripple rejection for I and Q VAGC = 0 to 3 V recommended value
at RF input; VAGC = 0 V - at RF input; VAGC = 0 V - at maximum gain; VAGC = 3 V in 22.5 MHz band - -
VAGC = 1.5 V; - Vo(p-p) = 750 mV; measured in baseband in 30 MHz band in 22.5 MHz band fripple = 60 MHz see Table 9 see Table 9 - - 30 - -
Gv(IQ)ripple td(g)(IQ)(R) RR60 3/4LO 5/4LO
- 5 - -40 -40
2 - - -35 -35
dB ns dB
Pulling sensitivity sensitivity to pulling on the third harmonic of the external VCO sensitivity to pulling on the fifth harmonic of the external VCO dBc dBc
VCO and synthesizer fosc n(osc) oscillator frequency range oscillator phase noise in the satellite band; foffset = 100 kHz; out of PLL loop bandwidth foffset = 1 and 10 kHz; fCOMP = 1 MHz with appropriate loop filter and charge pump setting 950 - - -100 2175 -94 MHz dBc/Hz
n
phase noise on baseband outputs
-
-
-78
dBc/Hz
2004 Sep 03
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Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
SYMBOL MDR Zosc fXTAL VXTOUT(p-p) PARAMETER main divider ratio crystal oscillator negative impedance (absolute value) crystal frequency AC output voltage on T2 = 1, T1 = 0, T0 = 0; pin XTOUT (peak-to-peak value) driving a load of CL = 10 pF, RL = 1 M crystal series impedance recommended value CONDITIONS MIN. 64 1.0 - 500 - 1.5 4 650 TYP.
TDA8260TW
MAX. 32767 - - -
UNIT k MHz mV
ZXTAL IL(CP) ILO(off) Vo
- -10 - 0.2
- 0 - -
200
nA A V
Charge pump output; pin CP charge pump leakage current T2 = 1; T1 = 1; T0 = 0 T2 = 0; T1 = 0; T0 = 1; Vtune = 33 V normal mode; Vtune = 33 V VBVS = VCC +10
Tuning voltage output; pin VT leakage current when pin VT is in high-impedance off-state output voltage when the loop is locked 10 32.7
Bus voltage select input; pin BVS ILIH ILIL VIL HIGH-level input leakage current - -100 - - - 0.46VCC 0.35VCC 0.6VCC - - -10 400 - - - - - - - - - - - - - - 100 - 0.2VCC 0.3VCC - - - 10 10 - - 0.4 A A V V V V V A A A kHz
LOW-level input leakage current VBVS = 0 V LOW-level input voltage pin BVS floating VBVS = 0 V VBVS = 5 V
SCL and SDA inputs 0.15VCC V
VIH
HIGH-level input voltage
pin BVS floating VBVS = 0 V VBVS = 5 V
ILIH
HIGH-level leakage current
VIH = 5.5 V; VCC = 5.5 V VIH = 5.5 V; VCC = 0 V VIL = 0 V; VCC = 5.5 V
ILIL fSCL(max) SDA output VACK AS input IIH IIL
LOW-level leakage current maximum input clock frequency
output voltage during acknowledge
Isink = 3 mA
V
HIGH-level input current LOW-level input current
VAS = VCC VAS = 0 V
- -10
- -
10 -
A A
2004 Sep 03
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Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
TDA8260TW
MGU797
MGU799
handbook, halfpage
68
handbook, halfpage
80
G (dB) 64
G (dB) 60
60
40
56
20
52 950
0 1150 1350 1550 1750 1950 f (MHz) 2150 0 1 2 VAGC (V) 3
Fig.3
Overall maximum gain as a function of frequency.
Fig.4 Overall gain as a function of AGC voltage.
MGU798
handbook, halfpage
20
handbook, halfpage
-70
MGU796
F (dB) 18
n (dBc/Hz)
-80
(1)
16 -90 14 -100 12
(2)
10 950
1150
1350
1550
1750
1950 2150 f (MHz)
-110 950
1150
1350
1550
1750 1950 f (MHz)
2150
(1) foffset = 10 kHz; fCOMP = 1 MHz. (2) foffset = 100 kHz; fCOMP = 1 MHz.
Fig.5
Noise figure at maximum gain as a function of frequency.
Fig.6
Phase noise on I and Q baseband outputs as a function of frequency.
2004 Sep 03
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Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
TDA8260TW
handbook, halfpage
0
MBL732
VIBBOUT VQBBOUT (dBc) -10
-20
-30
-40
0
20
40 foffset (MHz)
60
Fig.7 Baseband output filters.
Measurement method for pulling sensitivity
handbook, full pagewidth
RF SIGNAL wanted signal GENERATOR ANZAC RF SIGNAL unwanted signal GENERATOR TDA8260TW
SPECTRUM ANALYSER
MGU793
Fig.8 Test set-up.
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Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
Table 9 Test signal conditions for pulling measurements TEST 3/4LO test SIGNAL wanted unwanted local oscillator 5/4LO test wanted unwanted local oscillator FREQUENCY fw = 2161 MHz fuw = 1613 MHz fLO = 2150 MHz fw = 1761 MHz fuw = 2188 MHz fLO = 1750 MHz LEVEL -10 dBm -2 dBm - -10 dBm -2 dBm -
TDA8260TW
CONTENT (see Fig.9) fw = fLO + 11 MHz fuw = fLO x 3/4 + 500 kHz - fw = fLO + 11 MHz fuw = fLO x 5/4 + 500 kHz -
The level of the wanted and unwanted signals given in Table 9 are measured at the outputs of the RF signal generators. The sensitivity to pulling is measured in baseband by the difference expressed in dB () between the level of the wanted signal and the spurious signal that has been generated by pulling. The ANZAC reference is HH128.
handbook, halfpage
Vsignal
11 wanted signal
11.5 spurious signal
f (MHz)
MGU794
Fig.9 Baseband spectrum.
2004 Sep 03
15
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
APPLICATION INFORMATION
TDA8260TW
handbook, full pagewidth 4 MHz
C2 39 pF
X1
C38 39 pF
XT1 XT2
1 2 3 4 5 6 7 8 9 10
38 37 36 35 34 33 32 31 30 29
XTOUT SDA SCL AS CP VT
4 MHz
+5 V
VCC(PLL) PLLGND AGCIN BIASN RFGND1
C2 C1 12 nF 330 pF R1 4.7 k R10 22 k + 30 V
VAGC +5 V
BVS VCC(VCO) TKA TKB VCOGND CAP1 CAP2 IOUT BBGND2 IBBIN n.c. IBBOUT IIN C14 100 nF C15 220 nF C16 220 nF C31 220 nF R3 33 +5 V C21 82 pF L1 18 nH C22 82 pF R5 4.7 k D1 BB178 C3 330 pF R2 1.5 k
+5 V C3 RFIN 2.2 pF C10 2.2 pF
VCC(RF) RFA RFB RFGND2 LP1 C11 100 nF LP2 QOUT C12 220 nF BBGND1 QBBIN
TDA8260TW
11 12 13 14 15 16 17 18 19 HEATSINK 28 27 26 25 24 23 22 21 20
R4 4.7 k
+5 V
VCC(BB) QBBOUT C13 100 nF QIN
MGU795
Fig.10 Typical application circuit.
2004 Sep 03
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Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
TDA8260TW
handbook, full pagewidth
AGCIN 5 4 MHz clock 4 MHz INPUT MATCHING LNA RFA 9 TDA8260TW 21 18 IBBOUT QBBOUT I Q 12 14
PWM 30
TDA10086
MPEG2 TS
I2C-bus
I2C-bus
MGU792
Fig.11 Tuner configuration of the TDA8260TW.
Application design The performance of the application using the TDA8260TW strongly depends on the application design itself. Furthermore the printed-circuit board design and the soldering conditions should take into account the exposed die pad underneath the device, as this requires an optimum electrical ground path for electrical performance, together with the capability to dissipate into the application the heat created in the device. Philips Semiconductors can provide support through reference designs and application notes for TDA8260TW together with associated channel decoders. Please contact your local Philips Semiconductors sales office for more information. Wave soldering is not suitable for the TDA8260TW package. This is because the heatsink needs to be soldered to the printed-circuit board underneath the package but with wave soldering the solder cannot penetrate between the printed-circuit board and the heatsink.
2004 Sep 03
17
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
PACKAGE OUTLINE
HTSSOP38: plastic thermal enhanced thin shrink small outline package; 38 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
TDA8260TW
SOT633-3
D
E
A X
c y exposed die pad side HE vM A
Z
Dh
38
20
Eh
A2 A1
(A3)
A
pin 1 index
Lp L
1
e bp
19
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.80 A3 0.25 bp 0.30 0.19 c 0.20 0.09 D (1) 12.6 12.4 Dh 3.65 3.45 E (2) 6.2 6.0 Eh 2.85 2.65 e 0.65 HE 8.3 7.9 L 1 Lp 0.75 0.45 v 0.2 w 0.1 y 0.1 Z 0.6 0.2
8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT633-3 REFERENCES IEC --JEDEC --JEITA --EUROPEAN PROJECTION
ISSUE DATE 04-01-22
2004 Sep 03
18
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON-T and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Manual soldering
TDA8260TW
To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2004 Sep 03
19
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, USON, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L(8), PMFP(9), WQCCN..L(8) Notes not suitable not suitable(4) suitable not not recommended(5)(6) recommended(7)
TDA8260TW
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable
not suitable
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages.
2004 Sep 03
20
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
TDA8260TW
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 Sep 03
21
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
PURCHASE OF PHILIPS I2C COMPONENTS
TDA8260TW
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2004 Sep 03
22
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R25/02/pp23
Date of release: 2004
Sep 03
Document order number:
9397 750 13304

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